Over the last ten years, we have seen tremendous progress in technologies for formal verification of the behavior of RTL designs. Today, these formal technologies are vastly more thorough than ...

Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification ...

Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL ...

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...

In recent years, many longstanding assumptions about formal verification have been rendered obsolete by ever-improving technology. Applications such as connectivity checking have shown that formal can ...

MUNICH, Germany, TOKYO, and SUNNYVALE, Calif. – May 23, 2011 – OneSpin Solutions, an EDA company that provides innovative formal assertion-based verification solutions, today announced Quantify ...

VC Formal Datapath Validation application delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques The new app ...

Jasper Design Automation's JasperCore formal tool incorporates a capability called ProofGrid, which enables the tool to distribute a high-level proof across multiple processors on a multi-threaded ...

Traditionally, formal verification is used after the fact for bug hunting or design-rule checking. It has yet to be applied up front, where it would affect design decisions at the RTL coding stage.

SANTA CLARA, Calif.--(BUSINESS WIRE)--Calypto® Design Systems, Inc., the leader in sequential analysis technology, today announced version 6.0 of SLEC®, its Sequential Logic Equivalence Checking ...